Intel ® has four classes of FPGAs to meet market needs from the industry’s highest density and performance to the most cost effective:
Each FPGA series include different features, such as embedded memory, digital signal processing (DSP) blocks, high-speed transceivers, or high-speed I/O pins, to cover a broad range of end products. Intel ® FPGAs are ideal for a wide variety of applications, from high-volume applications to state-of-the-art products.
This application note uses the latest information available for the Intel ® Quartus ® Prime Pro Edition software version 17.1 and Xilinx* Vivado* Design Suite version 2017.2, supporting the latest programmable chips.
The last part of the chapter demonstrates how to translate device and design constraints. The following chapter provides guidelines to convert Vivado* designs to the Intel ® Quartus ® Prime Pro Edition software, including Xilinx* IP Catalog modules and instantiated primitives. The next chapter draws a parallel between the design flows in the Intel ® Quartus ® Prime Pro Edition software and Xilinx* Vivado* software, comparing features whenever possible. It further highlights unique features of Intel ® Stratix ® 10, Intel ® Arria ® 10, and Intel ® Cyclone ® 10 GX devices supported in the latest edition of the Intel ® Quartus ® Prime Pro Edition software. This application note starts with a description of the current Xilinx* and Intel ® FPGA technologies and compares devices available for three different process technologies. This document is intended for Xilinx* designers who are familiar with the Xilinx* Vivado* software and want to convert existing Vivado* designs to the Intel ® Quartus ® Prime Pro Edition software environment. In most cases, you can simply import your register transfer level (RTL) into the Intel ® Quartus ® Prime Pro Edition software and begin compiling your design to the target device. Document Revision History for Intel FPGA Design Flow for Xilinx Usersĭesigning for Intel ® Field Programmable Gate Array (FPGA) devices is similar, in concept and practice, to designing for Xilinx* FPGAs. Differences Between PBLOCK and Logic Lock Regions Setting Equivalent Xilinx Design Constraints Example: Converting to the Intel FPGA Multiply Adder IP core Example: Converting to the LPM_MULT IP Core Example: Converting Xilinx MMCM into an Intel PLL Converting Mixed-Mode Clock Manager (MMCM) to Phase-Locked Loop (PLL) Determining Memory Block and Mapping Ports Read-During-Write Operation at the Same Address Differences Between Xilinx Memory and Intel FPGA Memory The Intel Quartus Prime Tcl Console Window Running Tcl Commands Interactively from the Shell Running Tcl Commands Directly from the Command Line Running Scripts in Batch Mode from a Shell Running Scripts from the DOS or UNIX Prompt Scripting with Tcl in the Intel Quartus Prime Pro Edition Software
Additional Intel Quartus Prime Pro Edition Features Cross-Probing in the Intel Quartus Prime Pro Edition Software Simulation Models for Designs Containing LPMs or IP Cores Create Timing Constraints with the Timing Analyzer Text Editor Create Timing Constraints with the Timing Analyzer GUI Platform Designer System Integration Tool Programming and Configuration File Support in the Intel Quartus Prime Pro Edition Software FPGA Design Flow Using Command Line Scripting Hardware and Software Tools for FPGA Design Introduction to Intel FPGA Design Flow for Xilinx Users